LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
LIBRARY ALTERA; 
USE ALTERA.MAXPLUS2.ALL; 
ENTITY DEBOUNCING IS
 PORT(D_IN, CLK: IN STD_LOGIC; 
 DD1, DD0, QQ1, QQ0 : OUT STD_LOGIC; 
 D_OUT, D_OUT1: OUT STD_LOGIC ); 
END ENTITY DEBOUNCING ; 
ARCHITECTURE ART OF DEBOUNCING IS
 COMPONENT DCFQ IS
 PORT(CLK, CLRN, PRN, D: IN STD_LOGIC; 
 Q: OUT STD_LOGIC); 
END COMPONENT DCFQ; 
 SIGNAL VCC, INV_D : STD_LOGIC ; 
 SIGNAL Q0, Q1 : STD_LOGIC ; 
 SIGNAL D1, D0 : STD_LOGIC ; 
 BEGIN
 VCC <= '1' ; 
 INV_D <= NOT D_IN ; 
U1: DCFQ PORT MAP (CLK => CLK, CLRN => INV_D, PRN => VCC, D =>VCC , Q => Q0); 
 U2: DCFQ PORT MAP (CLK => CLK, CLRN => Q0, PRN => VCC, D =>VCC , Q => Q1); 
 PROCESS (CLK)
 BEGIN
IF CLK'EVENT AND CLK='1' THEN
 D0 <= NOT Q1; 
 D1 <= D0; 
END IF ; 
END PROCESS ; 
 DD0 <= D0; DD1 <= D1; QQ1 <= Q1; QQ0 <= Q0; 
 D_OUT <= NOT (D1 AND NOT D0); 
 D_OUT1 <= NOT Q1 ; 
END ARCHITECTURE ART;