LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY DCFQ IS
 PORT(CLK, CLRN, PRN, D: IN STD_LOGIC; 
 Q: OUT STD_LOGIC); 
END ENTITY DCFQ ; 
ARCHITECTURE ART OF DCFQ IS
 BEGIN
 PROCESS (CLK, CLRN, PRN)
 BEGIN
IF CLRN='0' AND PRN='1' THEN
 Q<='0'; 
 ELSIF CLRN='1' AND PRN='0' THEN
 Q<='1'; 
ELSIF CLK'EVENT AND CLK='1' THEN
 Q <=D; 
 END IF ; 
 END PROCESS ; 
END ARCHITECTURE ART;